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iso7420fcc sllsed3c ? june 2013 ? revised july 2015 iso7420fcc low-power dual channel digital isolator 1 features 3 description iso7420fcc provides galvanic isolation up to 2500 1 ? signaling rate: 50 mbps (5-v supplies) v rms for 1 minute per ul and 4242 v pk per vde. ? output is low in default mode this device has two isolated channels. each channel ? integrated noise filter on the input pins has a logic input and output buffer separated by a silicon dioxide (sio 2 ) insulation barrier. used in ? low power consumption: typical i cc per channel conjunction with isolated power supplies, this device ? 1.8 ma at 1 mbps, 3.9 ma at 25 mbps (5-v prevents noise currents on a data bus or other circuit supplies) from entering the local ground and interfering with or ? 1.4 ma at 1 mbps, 2.6 ma at 25 mbps (3.3-v damaging sensitive circuitry. the suffix f indicates supplies) low-output option in fail-safe conditions (see table 2 ). this device has integrated noise filter for harsh ? low propagation delay: 20 ns typical (5-v environments where short noise pulses may be supplies) present at the device input pins. ? channel-to-channel output skew: 2 ns maximum iso7420fcc has ttl input thresholds and operates ? 3.3-v and 5-v level translation from 2.7-v to 5.5-v supplies. all inputs are 5-v ? wide t a range specified: ? 40 c to 125 c tolerant when supplied from a 2.7-v or 3.3-v supply. ? 60-kv/ s transient immunity, typical (5-v device information (1) supplies) part number package body size (nom) ? low emissions iso7420fcc soic (8) 4.90 mm 3.91 mm ? isolation barrier life: > 25 years (1) for all available packages, see the orderable addendum at ? operates from 2.7-v to 5.5-v supply levels the end of the datasheet. ? narrow body soic-8 package ? safety and regulatory approvals simplified schematic ? 4242 v pk isolation per din v vde v 0884-10 (vde v 0884-10):2006-12 ? 2.5 kv rms isolation for 1 minute per ul 1577 ? csa component acceptance notice 5a, iec 60950-1 and iec 61010-1 end equipment standards ? gb4943.1-2011 cqc certification 2 applications ? opto-coupler replacement in: ? industrial fieldbus ? profibus ? modbus ? devicenet ? data buses ? servo control interface ? motor control ? power supplies ? battery packs 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. unless otherwise noted, this document contains production data. productfolder sample &buy technical documents tools & software support &community
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com table of contents 1 features .................................................................. 1 7 parameter measurement information ................ 10 2 applications ........................................................... 1 8 detailed description ............................................ 11 8.1 overview ................................................................. 11 3 description ............................................................. 1 8.2 functional block diagram ....................................... 11 4 revision history ..................................................... 2 8.3 feature description ................................................. 12 5 pin configuration and functions ......................... 3 8.4 device functional modes ........................................ 15 6 specifications ......................................................... 3 9 application and implementation ........................ 16 6.1 absolute maximum ratings ..................................... 3 9.1 application information ............................................ 16 6.2 esd ratings .............................................................. 3 9.2 typical application ................................................. 16 6.3 recommended operating conditions ....................... 4 10 power supply recommendations ..................... 19 6.4 thermal information .................................................. 4 11 layout ................................................................... 19 6.5 electrical characteristics: v cc1 and v cc2 = 5 v 10% ............................................................................ 5 11.1 layout guidelines ................................................. 19 6.6 electrical characteristics: v cc1 and v cc2 = 3.3 v 11.2 layout example .................................................... 19 10% ............................................................................ 5 12 device and documentation support ................. 20 6.7 electrical characteristics: v cc1 and v cc2 = 2.7 v .... 6 12.1 documentation support ........................................ 20 6.8 power dissipation characteristics ............................ 6 12.2 community resources .......................................... 20 6.9 switching characteristics: v cc1 and v cc2 = 5 v 12.3 trademarks ........................................................... 20 10% ............................................................................ 7 12.4 electrostatic discharge caution ............................ 20 6.10 switching characteristics: v cc1 and v cc2 = 3.3 v 12.5 glossary ................................................................ 20 10% ............................................................................ 7 13 mechanical, packaging, and orderable 6.11 switching characteristics: v cc1 and v cc2 = 2.7 v . 7 information ........................................................... 20 6.12 typical characteristics ............................................ 8 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (january 2014) to revision c page ? added pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 ? vde standard changed to din v vde v 0884-10 (vde v 0884-10): 2006-12 .................................................................... 1 ? changed vde standard changed to din v vde v 0884-10 (vde v 0884-10):2006-12 ...................................................... 1 ? changed note 1 figure 12 .................................................................................................................................................. 10 ? changed figure 13 .............................................................................................................................................................. 10 changes from revision a (july 2013) to revision b page ? changed the safety and regulatory approvals list ............................................................................................. 1 ? changed the v ih max value from: v cc to: 5.5v in the recommended operating conditions table ................... 4 ? changed the v pr and v iotm parameter from: din en 60747-5-2 to: din en 60747-5-5 in the insulation characteristics table ................................................................................................................................................... 13 ? changed the regulatory information table ............................................................................................................ 13 ? changed the title of figure 16 from: jc thermal derating curve per din en 60747-5-2 to: jc thermal derating curve per din en 60747-5-5 ............................................................................................................................................... 14 changes from original (june 2013) to revision a page ? changed high-level output voltage min value from: v ccx to: v cc2 ..................................................................................... 5 ? changed high-level output voltage min value from: v ccx to: v cc2 and removed note 1 ................................................... 5 ? changed high-level output voltage min value from: v ccx to: v cc2 and removed note 1 ................................................... 6 ? changed figure 3 x axis values ............................................................................................................................................ 8 2 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 5 pin configuration and functions iso7420: d package 8-pin soic top view pin functions pin i/o description name no. gnd1 4 ? ground connection for v cc1 gnd2 5 ? ground connection for v cc2 ina 2 i input, channel a inb 3 i input, channel b outa 7 o output, channel a outb 6 o output, channel b v cc1 1 ? power supply, v cc1 v cc2 8 ? power supply, v cc2 6 specifications 6.1 absolute maximum ratings see (1) min max unit v cc1 , v cc2 supply voltage (2) ? 0.5 6 v v io voltage at inx, outx ? 0.5 v cc + 0.5 (3) v i o output current ? 15 15 ma t j(max) maximum junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to network ground terminal and are peak voltage values. (3) maximum voltage must not exceed 6 v. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001 (1) 4000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22- 1500 c101 (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: iso7420fcc
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 6.3 recommended operating conditions min nom max unit v cc1 , v cc2 supply voltage 2.7 5.5 v high-level output current (v cc 3 v) ? 4 ma i oh high-level output current (v cc < 3 v) -2 ma i ol low-level output current 4 ma v ih high-level input voltage 2 5.5 v v il low-level input voltage 0 0.8 v 4.5-v operation 20 t ui input pulse duration ns < 4.5-v operation 25 4.5-v operation 0 50 mbps 1 / t ui signaling rate < 4.5-v operation 0 40 t j (1) junction temperature ? 40 136 c t a ambient temperature -40 25 125 c (1) to maintain the recommended operating conditions for t j , see the power dissipation characteristics table. 6.4 thermal information iso7420fcc thermal metric (1) d (soic) unit 8 pins r ja junction-to-ambient thermal resistance 115.1 c/w r jc(top) junction-to-case (top) thermal resistance 60.1 c/w r jb junction-to-board thermal resistance 56.4 c/w jt junction-to-top characterization parameter 17.2 c/w jb junction-to-board characterization parameter 55.8 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 4 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 6.5 electrical characteristics: v cc1 and v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 4 ma; see figure 12 . v cc2 ? 0.5 4.8 v oh high-level output voltage v i oh = ? 20 a; see figure 12 . v cc2 ? 0.1 5 i ol = 4 ma; see figure 12 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 12 . 0 0.1 v i(hys) input threshold voltage hysteresis 450 mv i ih high-level input current inx = v cc1 10 a i il low-level input current inx = 0 v ? 10 a cmti common-mode transient immunity v i = v cc1 or 0 v; see figure 14 . 25 60 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) i cc1 0.5 1.1 dc input: v i = v cc1 or 0 v, dc to 1 mbps ac input: c l = 15pf i cc2 3 4.6 i cc1 1 1.5 10 mbps i cc2 4 6 supply current for v cc1 and v cc2 ma i cc1 1.7 2.5 25 mbps c l = 15pf i cc2 6 8.5 i cc1 2.7 4 50 mbps i cc2 8.5 12 6.6 electrical characteristics: v cc1 and v cc2 = 3.3 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 4 ma; see figure 12 . v cc2 ? 0.5 3 v oh high-level output voltage v i oh = ? 20 a; see figure 12 . v cc2 ? 0.1 3.3 i ol = 4 ma; see figure 12 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 12 . 0 0.1 v i(hys) input threshold voltage hysteresis 425 mv i ih high-level input current inx = v cc1 10 a i il low-level input curre inx = 0 v -10 a cmti common-mode transient immunity v i = v cc1 or 0 v; see figure 14 . 25 40 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) i cc1 0.3 0.8 dc input: v i = v cc1 or 0 v, dc to 1 mbps ac input: c l = 15pf i cc2 2.4 3.3 i cc1 0.6 1.2 10 mbps i cc2 3.1 4.5 supply current for v cc1 and v cc2 ma i cc1 1 2 25 mbps c l = 15pf i cc2 4.2 6.1 i cc1 1.3 2.3 40 mbps i cc2 5.3 7.5 copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: iso7420fcc
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 6.7 electrical characteristics: v cc1 and v cc2 = 2.7 v t a = ? 40 c to 125 c parameter test conditions min typ max unit i oh = ? 2 ma; see figure 12 . v cc2 ? 0.3 2.5 v oh high-level output voltage v i oh = ? 20 a; see figure 12 . v cc2 ? 0.1 2.7 i ol = 4 ma; see figure 12 . 0.2 0.4 v ol low-level output voltage v i ol = 20 a; see figure 12 . 0 0.1 v i(hys) input threshold voltage hysteresis 350 mv i ih high-level input current inx = v cc1 10 a i il low-level input current inx = 0 v ? 10 a cmti common-mode transient immunity v i = v cc1 or 0 v; see figure 14 . 25 35 kv/ s supply current (all inputs switching with square wave clock signal for dynamic i cc measurement) i cc1 0.15 0.4 dc input: v i = v cc1 or 0 v, dc to 1 mbps ac input: c l = 15pf i cc2 2.1 3.1 i cc1 0.4 0.7 10 mbps i cc2 2.7 4 supply current for v cc1 and v cc2 ma i cc1 0.7 1.2 25 mbps c l = 15pf i cc2 3.6 5 i cc1 1 1.7 40 mbps i cc2 4.4 6.3 6.8 power dissipation characteristics iso7420fcc thermal metric d (soic) unit 8 pins v cc1 = v cc2 = 5.5 v, t j = 150 c, c l = 15 pf, p d device power dissipation 120 mw input a 50-mbps 50% duty-cycle square wave 6 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 6.9 switching characteristics: v cc1 and v cc2 = 5 v 10% t a = ? 40 c to 125 c parameter test conditions min typ max unit t plh , t phl propagation delay time 10 20 37 ns see figure 12 . pwd (1) pulse width distortion |t phl ? t plh | 2.5 5 ns t sk(o) (2) channel-to-channel output skew time 2 ns t sk(pp) (3) part-to-part skew time 12 ns t r output signal rise time 2.5 ns see figure 12 . t f output signal fall time 2.5 ns t gs pulse width of glitches suppressed by the input filter 12 ns t fs fail-safe output delay time from input data or power loss see figure 13 . 8 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.10 switching characteristics: v cc1 and v cc2 = 3.3 v 10% over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time 10 22 40 ns see figure 12 . pwd (1) pulse width distortion |t phl ? t plh | 3 ns t sk(o) (2) channel-to-channel output skew time 2 ns t sk(pp) (3) part-to-part skew time 19 ns t r output signal rise time see figure 12 . 3 ns t f output signal fall time 3 ns t gs pulse width of glithes suppressed by the input filter 12.5 ns t fs fail-safe output delay time from input power loss see figure 13 . 8 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.11 switching characteristics: v cc1 and v cc2 = 2.7 v t a = ? 40 c to 125 c parameter test conditions min typ max unit t plh , t phl propagation delay time 15 26 45 ns see figure 12 . pwd (1) pulse width distortion |t phl ? t plh | 3 ns t sk(o) (2) channel-to-channel output skew time 2 ns t sk(pp) (3) part-to-part skew time 22 ns t r output signal rise time 3 ns see figure 12 . t f output signal fall time 3 ns t gs pulse width of glitches suppressed by the input filter 13.5 ns t fs fail-safe output delay time from input power loss see figure 13 . 8 s (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: iso7420fcc
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 6.12 typical characteristics figure 1. supply current per channel vs data rate figure 2. supply current for both channels vs data rate figure 3. high-level output voltage vs high-level output figure 4. low-level output voltage vs low-level output current current figure 5. v cc1 and v cc2 undervoltage threshold vs free-air figure 6. propagation delay time vs free-air temperature temperature 8 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc 0 2 4 6 8 10 0 10 20 30 40 50 supply current (ma) data rate (mbps) icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v c002 i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5 v i cc2 at 5 v t a = 25 c c l = 15 pf 13 15 17 19 21 23 25 27 40 5 30 65 100 135 propagation delay time (ns) free-air temperature ( ? c) tplh at 3.3 v tphl at 3.3 v tplh at 5 v tphl at 5 v c006 t plh at 3.3 v t phl at 3.3 v t plh at 5 v t phl at 5 v 2.34 2.36 2.38 2.4 2.42 2.44 2.46 2.48 2.5 50 0 50 100 150 power supply under voltage threshold (v) free-air temperature ( ? c) vcc rising vcc falling c005 v cc rising v cc falling 0 1 2 3 4 5 6 C15 C10 C5 0 high-level output voltage (v) high-level output current (ma) vcc at 3.3 v vcc at 5 v c003 v cc at 3.3 v v cc at 5 v t a = 25 c 0 0.2 0.4 0.6 0.8 1 0 5 10 15 low-level output voltage (v) low-level output current (ma) vcc at 3.3 v vcc at 5 v c004 v cc at 3.3 v v cc at 5 v t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 10 20 30 40 50 supply current (ma) data rate (mbps) icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v c001 i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5 v i cc2 at 5 v t a = 25 c c l = 15 pf
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 typical characteristics (continued) figure 7. output jitter vs data rate figure 8. input glitch suppression time vs free-air temperature figure 9. eye diagram at 50 mbps, 5v at 25 c figure 10. eye diagram at 40 mbps, 3.3v at 25 c figure 11. eye diagram at 40 mbps, 2.7v at 25 c copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: iso7420fcc 0 0.2 0.4 0.6 0.8 1 1.2 0 20 40 60 pk-pk output jitter (ns) data rate (mbps) output jitter at 3.3 v output jitter at 5 v c007 t a = 25 c 0 2 4 6 8 10 12 14 16 18 40 15 10 35 60 85 110 135 input glitch rejection time (ns) free-air temperature ( ? c) tgr at 2.7 v tgr at 3.3 v tgr at 5 v c008 t gs at 2.7 v t gs at 3.3 v t gs at 5 v
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 7 parameter measurement information (1) the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 ? . at the input, a 50- resistor is required to terminate the input generator signal. it is not needed in actual application. (2) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 12. switching characteristic test circuit and voltage waveforms a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 13. fail-safe output delay-time test circuit and voltage waveforms (1) c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 14. common-mode transient immunity test circuit 10 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc isolation barrier c = 0.1 f 1% in v oh (1) or v ol out v cc1 + C v cm v cc2 c = 0.1 f 1% ! gnd2 gnd1 s1 + C pass-fail criteria C output must remainstable. c l ! v o out isolation barrier note a c l v i in = v cc 0 v t fs fs low v o v i 2.7 v 50% v cc v cc v ol v oh s0412-01 isolation barrier v i 50 w in v o input generator (1) c l (2) out 1.4 v 10% 90% v i v o t plh t phl 1.4 v v cc1 0 v v /2 cc t r t f v oh v /2 cc v ol
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 8 detailed description 8.1 overview the isolator in figure 15 is based on a capacitive isolation barrier technique. the i/o channel of the device consists of two internal data channels, a high-frequency channel (hf) with a bandwidth from 100 kbps up to 50 mbps, and a low-frequency channel (lf) covering the range from 100 kbps down to dc. in principle, a single- ended input signal entering the hf-channel is split into a differential signal via the inverter gate at the input. the following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. the comparator outputs drive a nor-gate flip-flop whose output feeds an output multiplexer. a decision logic (dcl) at the driving output of the flip-flop measures the durations between signal transients. if the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the dcl forces the output-multiplexer to switch from the high- to the low-frequency channel. because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (pwm) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. as the input is modulated, a low-pass filter (lpf) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 functional block diagram figure 15. conceptual block diagram of a digital capacitive isolator copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: iso7420fcc
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 8.3 feature description 8.3.1 insulation and safety-related specifications for soic-8 package over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit l(i01) minimum air gap (clearance) shortest terminal-to-terminal distance through air 4 mm minimum external tracking shortest terminal-to-terminal distance across the l(i02) 4 mm (creepage) package surface tracking resistance (comparative cti din en 60112 (vde 0303-11); iec 60112 > 400 v tracking index) dti distance through the insulation minimum internal gap (internal clearance) 0.014 mm v io = 500 v, t a = 25 c > 10 12 ? isolation resistance, input to r io output (1) v io = 500 v, 100 c t a 125 c > 10 11 ? barrier capacitance, input to c io v io = 0.4 sin (2 ft), f = 1 mhz 1 pf output (1) c i input capacitance (2) v i = v cc /2 + 0.4 sin (2 ft), f = 1 mhz, v cc = 5 v 1 pf (1) all pins on each side of the barrier tied together creating a two-terminal device. (2) measured from input pin to ground. note creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 12 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 8.3.2 insulation characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions specification unit din v vde v 0884-10 (vde v 0884-10):2006-12 (1) v iorm maximum working isolation voltage 566 v pk method a, after environmental tests subgroup 1, v pr = v iorm x 1.6, t = 10 s, 906 partial discharge < 5 pc method b1, v pr input-to-output test voltage v pr = v iorm x 1.875, t = 1 s (100% production test) 1062 v pk partial discharge < 5 pc after input/output safety test subgroup 2/3, v pr = v iorm x 1.2, t = 10 s, 680 partial discharge < 5 pc v test = v iotm v iotm maximum transient isolation voltage t = 60 sec (qualification) 4242 v pk t= 1 sec (100% production) r s isolation resistance v io = 500 v at t s = 150 c > 10 9 ? pollution degree 2 ul 1577 v test = v iso = 2500 v rms , t = 60 sec (qualification) v iso isolation voltage v test = 1.2 x v iso = 3000 v rms , t = 1 sec (100% 2500 v rms production) (1) climatic classification 40/125/21 table 1. iec 60664-1 ratings table parameter test conditions specification material group ii rated mains voltage 150 v rms i ? iv installation classification rated mains voltage 300 v rms i ? iii 8.3.3 regulatory information vde csa ul cqc certified according to din v vde approved under csa component recognized under ul 1577 v 0884-10 (vde v 0884- acceptance notice 5a, iec 60950- component recognition certified according to gb4943.1-2011 10):2006-12 and din en 61010- 1, and iec 61010-1 program 1 (vde 0411-1):2011-07 3000 v rms isolation rating; 400 v rms basic and 200 v rms reinforced insulation maximum basic insulation working voltage per csa 60950-1- maximum transient isolation basic insulation, altitude 5000m, 07+a1 and iec 60950-1 (2nd single protection, 2500 voltage, 4242 v pk ; tropical climate, 250 v rms maximum ed)+a1; v rms (1) maximum working isolation working voltage 300 v rms basic and 150 v rms voltage, 566 v pk reinforced insulation maximum working voltage per csa 61010-1- 12 and iec 61010-1 (3rd ed) certificate number: certificate number: 40016131 master contract number: 220991 file number: e181974 cqc14001109540 (1) production tested 3000 v rms for 1 second in accordance with ul 1577. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: iso7420fcc
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 8.3.4 safety limiting values safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. parameter test conditions min typ max unit ja = 115.1 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c 197 safety input, output, or supply i s ja = 115.1 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c 302 ma current ja = 115.1 c/w, v i = 2.7 v, t j = 150 c, t a = 25 c 402 t s maximum safety temperature 150 c the safety-limiting constraint is the absolute-maximum junction temperature specified in the absolute maximum ratings table. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information table is that of a device installed on a high-k test board for leaded surface-mount packages. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. figure 16. jc thermal derating curve per vde 14 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 safety limiting current (ma) case temparature ( ? c) c000 v cc1 = v cc2 = 2.7 v v cc1 = v cc2 = 5.5 v v cc1 = v cc2 = 3.6 v
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 8.4 device functional modes table 2. function table (1) input output v cc1 v cc2 ina, inb outa, outb h h pu pu l l open l (2) pd pu x l (2) x pd x undetermined (1) pu = powered up (v cc 2.7 v); pd = powered down (v cc 2.1 v); x = irrelevant; h = high level; l = low level (2) in fail-safe condition, output defaults to low level 8.4.1 device i/o schematics figure 17. device i/o schematics copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: iso7420fcc in 500 v cc1 v cc1 7.5 ua input v cc2 out output 8 13
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information iso7420fcc utilize single-ended ttl-logic switching technology. its supply voltage range is from 2.7 v to 5.5 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (i.e. c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application iso7420fcc can be used to isolate power mosfets from sensitive logic circuitry in switch mode power supplies (smps) as shown in figure 18 . low default output of iso7420fcc is critical for proper operation of power mosfets in such applications. figure 18. isolated switch mode power supply 9.2.1 design requirements unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the iso7420fcc only requires two external bypass capacitors to operate. 9.2.2 detailed design procedure 9.2.2.1 supply current equations 9.2.2.1.1 maximum supply current equations (calculated over recommended operating temperature range and silicon process variation). at v cc1 = v cc2 = 5 v 10%: i cc1 (max) = 1.1 + 5.80e-02 f (1) i cc2 (max) = 4.6 + 6.55e-02 f + 5.5e-03 f c l (2) at v cc1 = v cc2 = 3.3 v 10%: i cc1 (max) = 0.8 + 3.40e-02 f (3) i cc2 (max) = 3.3 + 4.60e-02 f + 3.6e-03 f c l (4) at v cc1 = v cc2 = 2.7 v: i cc1 (max) = 0.4 + 3.20e-02 f (5) i cc2 (max) = 3.1 + 3.75e-02 f + 2.7e-03 f c l (6) 16 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc iso7420fcc ucc27423 pwm mosfet a mosfet b
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 typical application (continued) f is data rate of each channel measured in mbps; c l is the capacitive load of each channel measured in pf; i cc1 (maximum) and i cc2 (max) are measured in ma. 9.2.2.1.2 typical supply current equations (calculated for t a = 25 c and nominal silicon process material). at v cc1 = v cc2 = 5 v: i cc1 (typical) = 0.5 + 4.40e-02 f (7) i cc2 (typical) = 3 + 3.50e-02 f + 5.0e-03 f c l (8) at v cc1 = v cc2 = 3.3 v: i cc1 (typical) = 0.3 + 2.60e-02 f (9) i cc2 (typical) = 2.4 + 2.25e-02 f + 3.3e-03 f c l (10) at v cc1 = v cc2 = 2.7 v: i cc1 (typical) = 0.15 + 2.10e-02 f (11) i cc2 (typical) = 2.1 + 1.75e-02 f + 2.7e-03 f c l (12) f is data rate of each channel measured in mbps; c l is the capacitive load of each channel measured in pf; i cc1 (typ) and i cc2 (typ) are measured in ma. figure 19. iso7420fcc typical circuit hook-up copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: iso7420fcc iso7420fcc 12 34 87 65 ina inb outa outb v cc2 0.1 f gnd2 0.1 f v cc1 gnd1
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com typical application (continued) 9.2.3 application curves figure 20 shows the ina input on channel 1 and outa output on channel 2 of an oscilloscope. figure 20. typical input and output waveforms 18 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
iso7420fcc www.ti.com sllsed3c ? june 2013 ? revised july 2015 10 power supply recommendations to ensure reliable operation at all data rates and supply voltages, a 0.1 f bypass capacitor is recommended at input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments' sn6501 . for such applications, detailed power supply design and transformer selection recommendations are available in sn6501 datasheet ( sllsea0 ). 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 21 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pf/in 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see application note digital isolator design guide , slla284 . 11.1.1 pcb material for digital circuit boards operating below 150 mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 epoxy-glass as pcb material. fr-4 (flame retardant 4) meets the requirements of underwriters laboratories ul94-v0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics. 11.2 layout example figure 21. recommended layer stack copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: iso7420fcc 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces , pads, and vias ground plane power plane low-speed traces high-speed traces
iso7420fcc sllsed3c ? june 2013 ? revised july 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? sn6501 transformer driver for isolated power supplies ( sllsea0 ) ? lvds application and data handbook ( slld009 ) ? digital isolator design guide ( slla284 ) ? isolation glossary ( slla353 ) 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks devicenet, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 20 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: iso7420fcc
package option addendum www.ti.com 24-mar-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples iso7420fccd active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 7420fc ISO7420FCCDR active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 7420fc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 24-mar-2015 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ISO7420FCCDR soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 24-mar-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ISO7420FCCDR soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 24-mar-2015 pack materials-page 2

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